A recent leak from the Geekbench synthetic test database indicates that AMD’s Zen 4 server processors will get 1MB of L2 cache per core. This is confirmed by tests of an engineering sample of one of the processors in the series. EPYC Genoa. Since AMD Ryzen desktop processors are made up of the same chiplets as EPYC server chips, having twice the L2 cache is likely to be true for Zen 4 Ryzen 7000 models as well.
The above Genoa series chip with OPN number 100-000000479-13 has 32 physical cores on board with support for 64 virtual threads, and operates at a base frequency of 1.2 GHz. Considering that this is a very early engineering sample, it is safe to assume that the market version of the processor will have a much higher frequency.
According to Geekbench, the tested chip has one megabyte of L2 cache per core, which is twice as much as Naples, Rome and Milan series EPYC processors. At the same time, the amount of L3 cache in the new chip has not changed compared to the same series of Milan processors and is 32 MB per chiplet (CCX block with eight cores). But since the Genoa-series processors will be able to offer up to 96 physical cores, the total amount of L3 cache will be higher than their predecessors in any case. The only exception will be fresh chips EPYC Milan-X with 3D V-Cache technology, which triples the amount of cache memory.
It should be recalled that the EPYC 7004 (Genoa) processors will be manufactured according to the 5nm process technology. They will be the first AMD server processors to support DDR5 RAM as well as PCIe 5.0. According to AMD, these chips should go on sale this year. Partners of the company are already receiving samples for testing.
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