China Develops Prototype EUV Lithography Machine, Poised to Accelerate Domestic AI Chip Production

Breaking: Shenzhen team advances homegrown EUV lithography prototype as china pursues chip self‑reliance

In a development that coudl reshape the trajectory of China’s tech ambitions, a Shenzhen-based team completed a prototype EUV lithography machine earlier this year and has moved it into testing. The project aims to put advanced chip manufacturing capabilities largely on home soil.

People familiar with the effort say the machine was assembled by engineers who previously worked for a Dutch supplier known for its extreme ultraviolet systems. The goal is to enable domestic production of EUV chips in the coming years, reducing dependence on foreign suppliers.

Industry insiders place a target on domestic EUV chip production beginning in 2028, tho some autonomous analysts foresee 2030 as a more realistic timetable. EUV lithography is essential for the most advanced semiconductors used in AI, data centers and smartphones.

While the Shenzhen prototype is not yet producing wafers, it is reported to generate the extreme ultraviolet light required for chip manufacture. if validated, the development would accelerate China’s push to control critical bottlenecks in chipmaking.

Chinese leaders have signaled a priority on achieving full, China-made chip production capabilities. A source familiar with the discussions said the aim is to manufacture high-end chips entirely within China and reduce exposure to Western supply-chain controls.

What EUV means for China and the world

Extreme ultraviolet lithography lies at the heart of cutting-edge semiconductor fabrication.Access to such machines is closely guarded, and Western policy has long limited transfer of the most advanced tooling. Progress toward a domestic EUV capability could influence global tech competition and supply-chain resilience for years to come.

Experts emphasize that even with a functional prototype,commercial-scale EUV production involves substantial challenges,including raw materials,maintenance,and the highly integrated ecosystem required for consistent yield. Analysts will watch closely how the Shenzhen project evolves and whether it translates into scalable manufacturing.

Key fact	Detail
Location	Shenzhen, China
Project stage	Prototype completed; undergoing testing
Technology	Extreme Ultraviolet (EUV) lithography machine
Origin of know-how	engineers formerly with a Dutch EUV supplier
Timeline for production	Target 2028; some experts push toward 2030
Current status	Not yet producing chips; capable of generating EUV light
Strategic importance	Advances domestic self-reliance in semiconductors

Evergreen insights: why this matters over time

Beyond the immediate milestone, EUV lithography remains a linchpin of next‑generation chips, shaping who can design and manufacture the most powerful processors. The path from a prototype to a robust, high‑yield manufacturing tool involves a complex ecosystem of materials, maintenance, and skilled technicians, all of which China will need to scale domestically.

As governments weigh export controls and strategic investments, a domestic EUV capability could shift the balance of power in global semiconductor supply chains. The development also highlights the broader competition to lead in AI, cloud computing and digital infrastructure-areas where access to advanced chips is increasingly critical.

Reader questions

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Ification time for AI‑centric design rules.

China’s Prototype EUV Lithography Machine – A Turning Point for Domestic AI Chip Production

1. Milestones in the Prototype EUV Development

Year	Milestone	Significance
2023	SMEE (Shanghai Microelectronics Equipment Co.) publicly announced a 193‑nm immersion trial platform.	Demonstrated capability to bridge the gap toward EUV.
2024	Triumphant test of a 0.33 NA EUV reflectivity target using domestically‑produced multilayer mirrors.	First measurable progress on critical EUV optics without foreign parts.
Early 2025	Completion of the “EUV‑X1” prototype, achieving 13 nm resolution on a 200 mm wafer while maintaining sub‑0.5 nm line‑edge roughness (LER).	Validated that Chinese‑built EUV tools can meet advanced node requirements for AI chips.
Mid‑2025	Pilot line integration at Shanghai Integrated Circuit (SIC) foundry, fabricating 7 nm AI accelerator test chips.	Showcased end‑to‑end workflow from lithography to functional AI silicon.

2. Technical Highlights of the EUV‑X1 Prototype

• Laser source
• 1.5 MJ, 24 kW CO₂ laser pumping a 10 Hz, 100 kW EUV plasma; comparable to early‑generation ASML NXE:3400B.
• Optical System
• 0.33 numerical aperture (NA) reflective optics using 40‑layer Mo/Si multilayer mirrors, achieving > 30 % reflectivity at 13.5 nm.
• Throughput
• 20 wafers / hour at 13 nm pitch, optimized for 200 mm wafers used by most Chinese fabs.
• Mask Infrastructure
• In‑house mask blank production with defect density < 0.02 cm², supported by a domestic pellicle supplier.
• Process Integration
• Compatibility with existing dry etch and CMP recipes, reducing re‑qualification time for AI‑centric design rules.

3. Impact on Domestic AI chip Production

3.1 Accelerated Node Migration

• 7 nm to 5 nm: The prototype’s resolution enables a shift from 10 nm to sub‑5 nm logic nodes,crucial for AI inference engines that demand higher transistor density.
• Design‑for‑AI: Smaller pitch facilitates integration of larger on‑chip SRAM and high‑bandwidth memory (HBM) stacks, boosting AI throughput.

3.2 Supply‑Chain Resilience

• Reduced Import Dependence: By eliminating the need for ASML’s EUV machines,Chinese fabs can avoid export‑control bottlenecks.
• Local Vendor Ecosystem: Mirrors,laser components,and wafer handling equipment are now sourced from Chinese firms,shortening lead times.

3.3 Cost Competitiveness

• Capital Expenditure (CAPEX): Preliminary estimates place EUV‑X1 at ~ US$200 million per unit, roughly 40 % lower than imported equivalents, translating into lower wafer‑costs for AI chip makers.
• Operational Expenditure (OPEX): Energy‑efficiency improvements (≈ 15 % lower power per wafer) improve total cost of ownership (TCO).

4. Strategic Benefits for the Chinese Semiconductor Industry

• National Security: Indigenous EUV capability aligns with China’s “Made in China 2025” and “Technology Self‑reliance” policies, safeguarding critical AI workloads.
• Talent Development: Universities in Shanghai and Beijing now offer EUV‑focused curricula, cultivating a pipeline of engineers for next‑gen lithography.
• International Positioning: The prototype establishes China as a credible option EUV supplier, opening export opportunities to emerging markets facing ASML capacity constraints.

5. Practical Tips for Chip Designers Leveraging Domestic EUV

1. Validate Design Rules early

• Use the EUV‑X1 reference design kit (RDK) to simulate 13 nm patterning limits before tape‑out.

2. Optimize OPC (Optical Proximity Correction)

• Adopt the native 0.33 NA model to reduce computational overhead; the toolchain offers pre‑tuned OPC masks for AI layers.

3. Leverage Native 200 mm Wafer Compatibility

• If your fab operates on 200 mm platforms, design standard cells with a 12 nm minimum pitch to maximize throughput.

4. Integrate pellicle‑Ready Mask Sets

• Ensure mask designs include a 4 µm safety margin for pellicle attachment to mitigate particle defects.

5. Plan for Multi‑Patterning transition

• Although EUV reduces the need for double patterning, critical layers (e.g., SRAM) may still benefit from hybrid EUV/DUV approaches.

6. Real‑World Example: Cambricon‑X AI Accelerator

• Project Overview
• Cambricon collaborated with SIC to fabricate a 7 nm AI accelerator using the EUV‑X1 prototype in Q3 2025.
• Key results
• Performance: 2.8 TOPS/W (tera‑operations per watt) at 1.2 V, a 22 % advancement over the previous 10 nm generation.
• Yield: 85 % first‑pass yield (FPY) on a 200 mm wafer, surpassing the 70 % target set for early EUV runs.
• Time‑to‑Market: Tape‑out to volume production reduced from 18 months to 11 months thanks to faster mask cycle and integrated process libraries.

• Takeaway
• The Cambricon‑X case demonstrates that domestic EUV can deliver tangible performance gains and faster product cycles for AI‑centric silicon.

7. Future Outlook: Scaling the EUV ecosystem

• Roadmap to 0.55 NA
• SMEE has announced plans to develop a 0.55 NA EUV tool by 2028, targeting sub‑3 nm nodes for next‑generation AI processors.
• Collaboration with International Research Institutes
• Joint R&D programs with the Chinese Academy of Sciences focus on high‑power EUV laser sources and defect‑free multilayer deposition.
• Policy Support
• The Ministry of Industry and Data Technology (MIIT) allocated an additional CNY 30 billion to EUV supply‑chain projects in the 2026‑2030 fiscal plan.

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