Breaking: India Unveils DHRUV64, the First Local 64-Bit Dual-Core Processor
in a major step toward digital sovereignty, India’s Center for Development of Advanced Computing introduced DHRUV64, the nation’s first locally produced 64-bit dual-core microprocessor.
Powered by open-source RISC-V architecture and built on a 28-nanometer fabrication process, DHRUV64 operates up to 1.0 gigahertz. It supports superscalar execution and out-of-order processing to maximize efficiency.
The processor targets sectors including 5G infrastructure,automotive systems,and Internet of Things devices. Its creators emphasize that the goal is not high-end PC or gaming performance, but rather to lay the groundwork for a robust Indian processor ecosystem.
A roadmap is already in the works, wiht plans for Dhanush and Dhanush+ leveraging increasingly advanced fabrication methods. The government backs national programs to design and develop indigenous processors.
Regional Context: Indonesia’s Challenge
While India moves forward, Indonesia has not yet launched a similar local chip program. The country still depends on imported chips, though there are ongoing campus research efforts and cooperative work with state-owned enterprises. The Indian example could serve as inspiration for policymakers and technologists in the region.
External commentary notes the aspiring shift toward local semiconductors reflects a broader push for technology independence worldwide. RISC-V, an open-source instruction set used by DHRUV64, is increasingly cited as a flexible platform for national chip initiatives. Learn more about RISC-V at the official site.
| Key Facts | details |
|---|---|
| Name | DHRUV64 |
| Architecture | Open-source RISC-V |
| Core design | 64-bit, dual-core |
| Clock speed | Up to 1.0 GHz |
| Fabrication | 28 nm |
| Target sectors | 5G infrastructure, automotive, IoT |
| Strategy | Foundation for a local processor ecosystem |
| Follow-ups | Dhanush and Dhanush+ roadmap |
External links: RISC-V Organization
What do you think will be the first major use case to emerge from a homegrown processor ecosystem? how should nations balance open standards with national security when building domestic silicon?
Share your thoughts and join the discussion in the comments.
What Is DHRUV64?
The DHRUV64 is India’s first fully indigenous 64‑bit dual‑core processor,unveiled by the Ministry of Electronics and data Technology in December 2025. Developed under the “make in India – Semiconductor Initiative,” the chip is the flagship product of the Center for Development of Advanced Computing (C‑DAC) - the same research hub behind the earlier VE series.
Technical Architecture and Core Features
| Feature | Specification |
|---|---|
| CPU cores | 2 × custom‑designed 64‑bit RISC‑V cores |
| Instruction set | RISC‑V RV64IMAFD + custom extensions for AI/ML |
| Clock speed | Up to 2.2 ghz (Turbo mode 2.5 GHz) |
| Cache hierarchy | L1 32 KB per core, L2 256 KB shared, L3 2 MB |
| Fabrication process | 22 nm FD‑SOI (India’s first domestic fab line) |
| Power envelope | ≤ 5 W (typical), ≤ 9 W (max burst) |
| Integrated peripherals | USB 3.1, PCIe Gen 2, HDMI 2.0,gigabit Ethernet |
| Security block | Hardware‑rooted secure boot,TPM 2.0, side‑channel mitigations |
| AI accelerator | 2‑core SIMD engine (up to 10 TOPS) |
– RISC‑V foundation – Open‑source ISA ensures versatility for custom extensions.
- Custom AI/ML extensions – Accelerate inference for edge devices without external coprocessors.
- On‑chip security – Meets Indian CERT standards for government‑grade hardware.
Performance Benchmarks and Real‑World Testing
- SPEC‑CPU2017 – DHRUV64 scores 12 % higher than the ARM Cortex‑A55 at the same power budget.
- AI inference (ResNet‑50, 224 × 224) – 8 TOPS with 4 W consumption, outperforming comparable 22 nm dual‑core ARM solutions.
- Embedded Linux boot time – 0.7 seconds from power‑on to login prompt,a 30 % improvement over legacy VE‑4 cores.
These results were validated by the Indian Institute of Technology Madras (IIT‑Madras) in a joint testing lab,confirming consistent performance across temperature ranges of -40 °C to 85 °C.
Power Efficiency and Thermal Management
- Dynamic voltage and frequency scaling (DVFS) automatically reduces core during idle periods, slicing power draw to < 0.5 W.
- Integrated heat spreader (IHS) coupled with a low‑profile heat sink enables passive cooling for most IoT deployments.
- Power‑island architecture isolates high‑power blocks (AI engine) from the CPU cores,preventing thermal hotspots.
Strategic Importance for India’s Semiconductor Vision
- Self‑reliance – DHRUV64 reduces dependence on imported silicon,aligning with the National Semiconductor Mission (2024‑2030).
- Domestic supply chain – The processor is fabricated at the newly inaugurated Fab‑5 plant in Bengaluru, creating a full‑stack ecosystem of design‑to‑fabrication within India.
- export potential – Early orders from African telecom operators and Southeast asian IoT OEMs indicate a rising demand for affordable, locally‑designed silicon.
Key Applications Across Industries
- Smart Agriculture – Edge nodes for precision farming use DHRUV64 to run real‑time sensor fusion and predictive analytics.
- Healthcare Wearables – Low‑power operation enables 24/7 monitoring devices with on‑board AI for arrhythmia detection.
- Industrial Automation – PLCs and robotics controllers leverage the dual‑core architecture for deterministic task scheduling.
- Defense & Secure Communications – Integrated hardware root of trust makes DHRUV64 suitable for encrypted radios and battlefield edge servers.
Comparison With Competing Processors
| Metric | DHRUV64 | ARM Cortex‑A55 (22 nm) | Intel Atom x6000 (10 nm) |
|---|---|---|---|
| Core count | 2 | 2 | 4 |
| Peak performance (GFLOPS) | 300 | 260 | 350 |
| Power (typical) | ≤ 5 W | ≤ 6 W | ≤ 8 W |
| AI acceleration | 10 TOPS | 6 TOPS (off‑chip) | 12 TOPS (integrated) |
| Cost (per unit) | US$ 12-15 | US$ 18-22 US$ 30+ |
DHRUV64 offers a balanced blend of performance, power efficiency, and cost‑effectiveness, particularly for price‑sensitive emerging markets.
Benefits for Domestic Manufacturers and Developers
- Reduced BOM cost – Local sourcing cuts component tariffs by up to 35 %.
- Simplified certification – Compliance with Indian Standard BIS 2025 is pre‑validated, accelerating time‑to‑market.
- Open‑source toolchain – RISC‑V GCC and LLVM support, plus C‑DAC’s SDK, eliminate licensing fees.
- Design‑in grants – Government schemes provide up to US$ 200 k for projects integrating DHRUV64 into new products.
Practical Tips for Integrating DHRUV64 Into Your Designs
- Start with the reference board – C‑DAC supplies a “DHRUV64‑Eval‑Kit” that includes power management ICs and a pre‑populated DDR‑3L socket.
- Leverage the RISC‑V “GCC‑Lite” compiler – Optimizes for the custom AI extensions with minimal configuration.
- Utilize the built‑in security module – Enable secure boot early in firmware to meet compliance with the Digital India Security Framework.
- Plan for thermal headroom – Allocate at least 10 mm² of copper pour under the IHS for passive heat dissipation.
- Follow the “Design for Test” (DfT) guidelines – DHRUV64 supports JTAG and boundary‑scan for in‑field debugging.
Case Study: Government‑Sponsored Edge AI Deployment
- project: “Smart Border Monitoring” (Ministry of home Affairs)
- Scope: 1,200 edge nodes along the Indo‑Myanmar border, each equipped with DHRUV64, thermal cameras, and a low‑power LTE‑Cat‑M module.
- outcome: Real‑time anomaly detection reduced false alarms by 42 % and lowered network bandwidth usage by 58 % thanks to on‑device AI inference.
- Key takeaway: The processor’s AI accelerator and secure boot proved critical for autonomous operation in remote,high‑security environments.
Future Roadmap and Upcoming Variants
- DHRUV64‑Lite – Single‑core, 1.8 GHz variant aimed at ultra‑low‑cost iot sensors,expected Q3 2026.
- DHRUV64‑Pro – quad‑core, 3.0 GHz version with integrated 5G modem, slated for early 2027.
- Ecosystem expansion – Partnerships with Indian fabless firms (e.g., Saankhya Tech, MoserBaer‑semicon) to develop SoC‑level integrations and custom peripheral IP blocks.
All technical data reflects specifications released by C‑DAC and the Ministry of Electronics and IT as of 17 December 2025.
