Google has teamed up with AMD to develop a 10th-generation Tensor Processing Unit (TPU), according to market intelligence notes from SemiAnalysis published in August 2026. This collaboration marks AMD’s first major involvement in a custom AI ASIC project, signaling a strategic shift toward hybrid architectures that combine proprietary accelerator technology with on-package general-purpose CPU cores to handle demanding reinforcement learning workloads.
The Shift Toward Hybrid TPU Architectures
For years, Google relied on Broadcom as its silicon designer for nine generations of proprietary AI accelerators, utilizing traditional configurations of tensor compute chips paired with separate host processors. However, the computational profile of modern artificial intelligence is changing. While conventional large language model (LLM) training remains overwhelmingly accelerator-bound, advanced reasoning and agentic models rely heavily on reinforcement learning. These specific computational paths demand massive general-purpose processing power located immediately adjacent to the tensor cores.
According to research from SemiAnalysis, Google and its cloud customers are actively pushing for TPUs equipped with on-package CPU cores to reduce latency and power consumption during reinforcement learning routines. By bridging the physical distance between general-purpose logic and tensor operations, hardware engineers can eliminate bottlenecks that traditionally plague multi-chip server clusters.
Why Google Brought in AMD
Google hardly needs an external partner to design a conventional tensor processor, given its deep in-house expertise. Yet, implementing a hybrid design requires specialized engineering capabilities that few firms possess at scale. Market intelligence indicates that AMD’s primary value proposition lies in its advanced packaging technologies, such as Silicon Interconnect Fabric (SoIC), and its data-center-grade design experience.
AMD already manufactures the Instinct MI300A, a complex accelerated processing unit that tightly integrates x86 CPU cores, accelerator chiplets, and High Bandwidth Memory (HBM) into a single package. This architectural background makes AMD a logical collaborator for a custom ASIC project requiring dense integration of heterogeneous silicon. While Intel maintains a broad strategic relationship with Google, Intel lacks direct experience in delivering production-ready, hybrid x86-plus-accelerator enterprise silicon architectures.
Evolving CPU-to-Accelerator Ratios in the Data Center
The architectural shift toward tighter integration is already visible in Google’s recent hardware deployment cycles. Previous infrastructure generations relied on an asymmetric compute ratio. Servers running Google’s 7th-generation TPUs allocated one Intel Xeon Emerald Rapids processor for every four accelerator units.
That balance shifted dramatically with the rollout of inference-oriented TPU 8i systems, which integrate one custom-designed Google Axion CPU for every two TPU units. Industry analysts suggest that optimal performance for upcoming reasoning models may require a strict 1:1 ratio of CPUs to accelerators. Bringing CPU cores directly onto the TPU package represents the physical realization of this trend.
Market Implications and Future Outlook
The collaboration highlights a broader industry acknowledgment that standard, standalone tensor chips face architectural limits when forced to execute complex, multi-step agentic workflows.
Although the exact distribution of intellectual property and the final form factor of the rumored TPU v10 family remain unconfirmed, the engagement itself demonstrates that Google is willing to look outside its proprietary manufacturing ecosystem to solve the scaling limits of next-generation AI workloads.
