Memory heavyweights SK hynix and Sandisk have formally released the first open technical specification for High-Bandwidth Flash through the Open Compute Project at the 2026 FMS Conference in Santa Clara, California. The new standard aims to bypass memory bottlenecks in enterprise artificial intelligence infrastructure by stacking NAND flash to expand capacity near accelerators.
Breaking the AI Memory Wall With Open Standardization
As parameter counts for frontier neural networks expand beyond hundreds of billions into the trillions, raw High Bandwidth Memory capacity on accelerator packages has become a critical financial and physical bottleneck. While HBM supplies the extreme multi-terabyte-per-second throughput necessary to feed modern tensor processing units, its high cost and physical interposer footprint strictly limit the total capacity engineers can connect to a graphics processing unit. To resolve this economic mismatch, memory titans SK hynix and Sandisk formally released the first open technical specification for High-Bandwidth Flash (HBF) through the Open Compute Project at the Future of Memory and Storage conference.
Developed in tandem with key ecosystem partners including Google DeepMind and Tenstorrent, the new specification inserts an intermediate, high-density memory tier directly between power-dense HBM and standard peripheral component interconnect express-attached solid-state drives. Alper Ilkbahar, chief technology officer at SanDisk, discussed the initiative at the 2026 FMS Conference in Santa Clara, California, noting that the company is pursuing HBF alongside SK hynix and others.
The technology stacks and connects NAND chips in a manner similar to how DRAM chips are stacked and connected in HBM. This results in a higher-performance NAND package that provides high non-volatile storage capacities to supplement or replace HBM depending upon the application.
Technical Architecture and Interface Design
The architecture relies on high-density three-dimensional and four-dimensional NAND flash technology packed into dense eight-high or sixteen-high stacked die configurations. According to technical disclosures from the conference, this configuration provides up to 512GB of near-compute capacity per stack based on two stack configurations. Bandwidth is categorized into three distinct grades, delivering scalable performance from approximately 0.4TB/s to 3.0TB/s.
To achieve near-RAM-class latencies and massive interconnect throughput, the specification mandates Universal Chiplet Interconnect Express (UCIe) as its physical and protocol-level host interface. The HBF specification adopted the UCIe interconnect to link HBF packages directly to processors.
By utilizing UCIe chiplet packaging rather than board-level traces or PCIe lanes, HBF die stacks sit directly on the same silicon interposer or high-density organic substrate as the host GPU or custom application-specific integrated circuit. When integrated with cutting-edge flash architectures like SK hynix’s 375-layer V10 4D NAND, HBF promises up to two and a half times greater power efficiency compared to standard server flash.
Addressing Inference Workloads and Economic Realities
Industry executives emphasized that the architecture targets specific demands in artificial intelligence inference. Kim Chunsung, executive vice president at SK hynix, outlined two types of storage requirements for inference running on personal devices: persistent assets such as models, retrieval-augmented generation, and user data, alongside dynamic runtime states required to store key-value caches, agent states, and metadata.
For enterprise workloads featuring Mixture of Experts topologies or per-layer embedding offloading, HBF allows accelerators to offload massive parameter sets that exceed HBM limits without suffering the severe latency and throughput penalties of the PCIe bus. In MoE architectures, only a fraction of total network parameters are active for any given token, leaving vast reservoirs of conditionally routed expert weights resident in fast memory. Because AI model serving is overwhelmingly a read-heavy operation where static model weights are retrieved repeatedly during matrix multiplication, the fundamental write endurance constraints of NAND flash are rendered virtually irrelevant.
Despite the performance gains, hardware enthusiasts wondering whether the ultra-dense memory will trickle down to desktop systems face a firm restriction.
“not anytime soon.”
Hothardware reporting
The structural realities of HBF rely heavily on advanced 3D heterogeneous packaging, silicon interposers, and dedicated UCIe physical layers that drive costs to levels only enterprise data center economics can absorb.
Consortium Roadmap and Market Forecasts
The HBF Consortium announced Jim Keller, CEO of Tenstorrent, as a new member of the consortium board joining David Patterson from Berkeley and Raja Koduri, founder and CEO of Oxmiq Labs. The organization outlined a clear deployment timeline following the release of the initial specification.
The full HBF specification is expected to arrive in early 2027, with physical samples becoming available in early 2028 and full flash production scheduled thereafter.
