NVIDIA is deploying its custom Vera CPU across internal electronic design automation (EDA) workflows to accelerate the development of next-generation processors.
The Bottleneck at the Heart of Silicon Engineering
Modern chip design is a relentless exercise in managing exponential complexity. While GPUs and AI accelerators handle massive parallel processing workloads, the foundational stages of semiconductor development remain tethered to CPU performance. Long before physical manufacturing or tapeout, engineering teams spend years validating register-transfer level (RTL) behavior. They must identify rare corner cases and execute thousands of iterations to ensure functional correctness.
Logic simulation, formal verification, and digital implementation depend heavily on single-core throughput, efficient memory subsystems, and low latency. Without high-performing CPUs driving these electronic design automation tools, verification bottlenecks stall the entire development pipeline. The speed of chip production dictates the cadence of the wider technology industry. When verification runs take days instead of hours, the delay ripples across the entire hardware roadmap.
To break through this bottleneck, NVIDIA is embedding its custom NVIDIA Vera CPU directly into its own EDA workflows. Vera is designed specifically to tackle these compute-heavy engineering demands.
Unpacking the Architecture of the Vera CPU
Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem. This layout is paired with a second-generation NVIDIA Scalable Coherent Fabric.
The engineering rationale here is straightforward. Modern EDA workloads often alternate between latency-sensitive single-threaded tasks and massive regression testing spread across distributed compute farms. The LPDDR5X memory subsystem and the Scalable Coherent Fabric ensure that memory bandwidth keeps pace with core execution demands. This minimizes stalls during heavy verification passes.
By shortening individual verification runs, engineers can evaluate a wider pool of design alternatives. They can complete comprehensive validation passes within the same strict product development windows.
Early Benchmarks With Cadence and Synopsys
NVIDIA’s initial testing of the Vera CPU involves close collaborations with industry mainstays Cadence and Synopsys, optimizing critical EDA applications for the new architecture.
The testing focuses on two distinct, highly demanding pillars of verification:
- Cadence Jasper: A formal verification platform utilizing smart proof technology and machine learning to isolate bugs early in the design cycle.
- Synopsys VCS: A high-performance functional verification solution designed to simulate complex chip behavior prior to physical fabrication.
When running identical core counts during early evaluations, both applications demonstrated up to 1.5x higher performance on selected production-class workloads. Beyond raw benchmarks, NVIDIA, Cadence, and Synopsys are engaged in deep application profiling and system-level tuning. The goal is to scale these productivity gains across a broader range of semiconductor workflows.
As Cadence and Synopsys adapt their software to modern high-core-count architectures, the entire semiconductor ecosystem benefits from faster convergence times.
Closing the Loop on Next-Generation Silicon
Deploying Vera internally is just the first step in a multi-generation strategy. NVIDIA has already outlined its roadmap, planning to build upon Vera with the upcoming Rosa CPU, which will be powered by the NVIDIA Rigel core.
This strategy creates an uninterrupted feedback loop. NVIDIA uses its own high-performance CPUs to design future CPUs and GPUs, refining both silicon architecture and software optimization simultaneously.
