2023-12-28 13:15:00
Alphawave, a silicon IP supplier and chip designer, conducted a verification test to demonstrate the interoperability of its PCIe 6.0 controller and physical interface with the company’s Keysight evaluation equipment.
According to information from the Tom’s Hardware website, in the test, the Alphawave managed to achieve a data transfer rate of 64 GT/s. In this way, Alphawave is ready to build chips with a PCIe 6.0 interface, just like other companies.
This Alphawave silicon implementation not only works with Keysight’s Protocol Exerciser at full speed with pulse amplitude modulation with four-level signaling (PAM4), but also supports the industry-first CXL 2.0.
According to the website Tom’s Hardware, a implementation also supports PCIe Gen6 Forward Error Correction (FEC), FLIT mode, and other features of the new interconnect standard. Additionally, the platform can be expanded with the CXL 3.0 protocol.
“Testing and measurement are critical aspects of interoperability, enabling Alphawave Semi to bring our products and customer solutions to market faster,” commented Letizia Giuliano, Vice President of IP Product Marketing at Alphawave Semi.
Finally, the company stated that its PCIe subsystem is extremely power efficient, offers low latency and “is built on the industry’s most successful PAM4 SerDes IP.” The expectation is that the standard will reach the market in 2024.
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