Renesas Electronics Corporation unveiled three modern System-on-Chip (SoC) technologies designed for automotive multi-domain electronic control units (ECUs), addressing the increasing demands for advanced AI processing, scalability, and functional safety. The technologies were presented at the International Solid-State Circuits Conference (ISSCC) 2026, held February 15–19 in San Francisco, USA.
The advancements approach as the automotive industry shifts towards software-defined vehicles (SDVs), requiring SoCs capable of handling multiple applications simultaneously while maintaining stringent safety standards. Renesas’s new technologies focus on enabling chiplet architectures that support functional safety, improving AI processing capabilities, and enhancing power control for greater efficiency and reliability.
A key innovation is a new chiplet architecture designed to meet Automotive Safety Integrity Level D (ASIL D) requirements, even in configurations utilizing multiple chiplets. This was achieved by combining the standard die-to-die UCIe interface with a proprietary RegionID mechanism. This prevents interference between hardware resources when numerous applications are running concurrently, ensuring Freedom from Interference (FFI). Conventional UCIe interfaces lack the ability to transmit RegionIDs between dies; Renesas solved this by mapping RegionIDs into physical address space and encoding them within the UCIe region, allowing for safe access control through the memory management unit (MMU) and real-time cores.
Testing confirmed the UCIe interface achieves a transmission speed of 51.2 GB/s, approaching the upper limit of intra-SoC transfer speeds, while maintaining bandwidth from processors to the memory bus. This combination of scalability and safety is intended to support high-performance automotive SoCs.
Renesas also developed a 3nm SoC design that enhances the performance of neural processing units (NPUs) for AI processing while maintaining automotive-grade quality. The increasing size of NPUs – expanding 1.5-fold compared to previous generations – has led to increased clock latency. To address this, Renesas redesigned the clock architecture by distributing clock pulse generators (CPGs) from the module level to the sub-module level, creating mini-CPGs (mCPGs). This significantly reduces clock latency and meets timing requirements.
Achieving zero defects in automotive applications requires precise test clock synchronization, which is complicated by multi-layer mCPGs. Renesas integrated test circuits into the hierarchical CPG architecture and unified the signal path for user and test clocks. The design synchronizes upper- and lower-level mCPGs under a single clock source during test mode, enabling unified phase adjustment. This approach allows Renesas to achieve quality aligned with zero-defect expectations, even for large-scale SoCs.
To improve power efficiency and safety, Renesas developed advanced power gating technology utilizing over 90 power domains, enabling precise power control ranging from milliwatts to tens of watts. The company also split power switches (PSWs) into ring PSWs and row PSWs to reduce IR drops associated with increasing current density in smaller process geometries. Ring PSWs suppress rush currents when power is turned on, while row PSWs equalize impedance within the domain, reducing IR drops by approximately 13% compared to conventional designs.
Meeting ASIL D functional safety standards, the dual core lock step (DCLS) configuration employs independent power switches and controllers for both master and checker cores. This allows for failure detection through lockstep operation, even if one side malfunctions. Loopback monitoring of each PSW’s gate signal detects OFF states in case of failure, and a digital voltage meter (DVMON), resistant to temperature drift, is used for voltage monitoring, improving aging tolerance by 1.4 mV.
These technologies are currently integrated into Renesas’s R-Car X5H SoC for automotive multi-domain ECUs. Renesas states the R-Car X5H will accelerate the evolution of SDVs, enabling autonomous driving and advanced digital cockpit features while ensuring safety.
