Taiwan Semiconductor Manufacturing Company (TSMC) has demonstrated a new method to produce smaller, faster chips without relying on ASML’s most advanced and expensive extreme ultraviolet (EUV) lithography tools, marking a significant development in semiconductor manufacturing.
The breakthrough, revealed during a technical briefing in April 2026, shows TSMC can achieve performance gains comparable to those expected from ASML’s high-numerical-aperture (high-NA) EUV systems by optimizing its existing deep ultraviolet (DUV) lithography processes through innovative patterning techniques and material science advancements.
According to TSMC officials, the approach allows the company to continue advancing its N2 and upcoming A16 process nodes using current-generation tools, potentially reducing capital expenditure and easing supply chain pressures tied to ASML’s high-NA EUV systems, which each cost over $300 million and face limited availability.
Technical Innovation Behind the Advance
TSMC’s method combines multiple patterning steps with refined resist materials and improved etch precision to achieve finer feature resolution than previously possible with DUV alone. By leveraging computational lithography and AI-driven process optimization, the company claims it can effectively extend the capabilities of 193nm immersion DUV tools to support logic chips with transistor densities approaching those of 2nm-class designs.
Dr. Jason Wang, TSMC’s Vice President of Fab Technology, explained during the briefing that the technique does not replace EUV but rather complements it, allowing for selective use of advanced lithography only where absolutely necessary. “We’re not eliminating the need for EUV,” Wang said. “We’re being smarter about when and where we deploy it, using DUV innovations to handle layers that previously required more expensive tools.”
The approach builds on TSMC’s existing leadership in semiconductor process innovation, where it has consistently pushed the limits of existing equipment through what the industry calls “more Moore” strategies—extracting additional scaling benefits from current tools before transitioning to the next generation.
Industry Implications and Market Response
Analysts note that if TSMC can reliably deliver N2- and A16-class performance using optimized DUV flows, it could alter the competitive dynamics in the foundry market. Companies like Samsung and Intel, which are also investing heavily in high-NA EUV, may face increased pressure to justify similar investments if TSMC achieves comparable results at lower cost.
ASML has not publicly commented on TSMC’s specific claims, but the company continues to emphasize that high-NA EUV remains essential for the most advanced logic and memory devices beyond 2027, particularly for applications requiring the highest levels of precision and throughput.
TSMC has not disclosed which customers are early adopters of the new flow, but sources indicate that initial production runs are underway for select high-performance computing and mobile applications, with volume production expected to begin in late 2026.
What Comes Next
TSMC plans to present further data on yield, performance, and power efficiency at the upcoming IEEE International Electron Devices Meeting (IEDM) in December 2026. The company will also detail how the new process integrates with its 3D chip-stacking technologies, such as SoIC (System-on-Integrated-Chips), which rely on fine interconnects that benefit from advanced patterning.
For now, the development underscores TSMC’s strategy of maximizing existing infrastructure even as preparing for future transitions—a balance that could influence how the semiconductor industry manages the rising costs of staying at the forefront of Moore’s Law.
Stay informed on the latest in semiconductor innovation. Share this article and join the conversation in the comments below.
