Google has deployed its first confidential TPU, the 8tx, by pairing its eighth-generation accelerator silicon with 5th Gen AMD Epyc “Turin” processors.
The move shows a strategic reliance on x86 architecture for secure AI workloads, bypassing Google’s proprietary Axion chips to use AMD’s established hardware-enforced trust boundaries.
Choosing Epyc Over Axion
When Google launched its eighth-generation TPU family in April 2026, it bifurcated the hardware into the TPU 8t for training and the TPU 8i for inference. While the ecosystem was built to scale, the introduction of the TPU 8tx on November 9, 2026, reveals a critical dependency: Google’s audited confidential computing stack currently mandates x86 architecture.
By selecting AMD Epyc, Google bridges its TPU accelerators with AMD’s Secure Encrypted Virtualization (SEV), allowing for hardware-enforced isolation of model weights and sensitive data during inference.
Google has not provided a timeline for porting this capability to its own Neoverse V2-based Axion processors. The omission is telling; Google’s official documentation for Confidential VM configurations remains restricted to AMD SEV and Intel TDX instances. As TechRadar reported, the firm’s existing security infrastructure is heavily vetted against these x86 foundations, making the integration of a new, unproven ARM-based security stack a difficult engineering hurdle.
Mark Lohmeyer, who runs AI and computing infrastructure at Google Cloud, told reporters that select customers will be able to deploy the 8tx in their own data centers, Data Center Knowledge reported, noting that Oracle recently said it will offer TPUs on its cloud. INSIDE quoted Lohmeyer arguing that the technology lowers the risk of physical operators reaching sensitive data, even in third-party facilities.
AMD Epyc Processors Align with TPU 8tx PCIe Gen5 Interface
The decision to utilize AMD’s 5th Gen Epyc processors is not merely a matter of security firmware but one of bandwidth alignment. The TPU 8tx requires a host capable of matching the TPU 8t’s PCIe Gen5 x16 interface.
According to reports from ServeTheHome, Google opted for the Turin series because a more advanced host, such as AMD’s 2nm Venice platform, would provide no tangible gains in accelerator bandwidth under the current design constraints.
The system inherits the 12.6 petaflops of FP4 compute and 216GB of HBM from the TPU 8t, while adopting the lower-latency Boardfly network architecture used by the TPU 8i. This configuration is specifically tailored for regulated enterprises and government entities that require the ability to fine-tune or distill AI agents on private data without risking exposure during the compute cycle.
Performance and Trust Metrics
- Compute Capacity: 12.6 petaflops of FP4 compute per 8tx unit.
- Memory: 216GB of High Bandwidth Memory (HBM).
- Host Integration: 5th Gen AMD Epyc “Turin” via PCIe Gen5 x16.
- Security Foundation: AMD Secure Encrypted Virtualization (SEV).
The Future of Hardware Attestation
As TPUs move beyond the walls of Google’s own data centers—with Oracle recently signaling plans to offer them on its cloud—the importance of hardware attestation grows.
The 8tx system functions as a trust anchor, ensuring that model owners can place proprietary weights on hardware operated by third parties. By embedding AMD silicon at the heart of this trust model, Google effectively makes AMD a silent partner in its off-campus security strategy.
Market speculation continues to swirl regarding a deeper integration between the two companies. A report from SemiAnalysis previously suggested that Google might be collaborating with AMD on a future “v10” generation of TPU hardware, potentially featuring integrated CPU cores on the same package. While the 8tx configuration keeps the CPUs and accelerators in separate sockets, it establishes a functional precedent for closer cooperation.
Whether Google will eventually move its confidential computing stack to its Axion line remains an open question. For now, the company has prioritized the immediate, audited security of the x86 ecosystem over the vertical integration of its custom silicon.
The TPU 8tx will be available to select customers for deployment in their own data centers, with the industry waiting to see how the platform performs under rigorous, real-world penetration testing once the systems reach scale.
