IBM has revealed an unreleased 2-nanometer processor architecture designed to execute Arm, IBM Z, and LinuxONE instructions concurrently on single high-performance cores. Slated to arrive by 2028, the multi-architecture chip aims to bridge enterprise-grade mainframe reliability with the expansive open-source Arm developer ecosystem.
Engineering a Dual-Architecture Microprocessor
Big Blue is breaking away from decades of architectural isolation. The upcoming chip combines 11 high-performance cores operating at more than 5.7 GHz on a cutting-edge 2-nanometer node. Each core features native instruction set execution for both Arm and IBM Z or LinuxONE environments simultaneously.
Mainframes have historically occupied a distinct corner of enterprise computing. While platforms like the IBM z17—delivered in 2025 on a standard three-year hardware cadence—offer unmatched reliability and virtualization, they operate outside mainstream software targets. The Arm ecosystem, by contrast, supports more than 22 million developers worldwide. According to IBM’s Vice President for the zSystems Ecosystem Meredith Stowell, that massive footprint encompasses a rapidly growing portfolio of cloud-native, AI, analytics, and infrastructure applications.
By bringing Arm instructions directly onto the silicon alongside Z instructions, IBM is attempting to solve a severe friction point for enterprise IT. Migration away from mainframes is notoriously expensive and risky due to decades of operational practice and data gravity. Yet hyperscalers and modern developers favor Arm-based infrastructure because open-source tools default to it. This new silicon design bridges that divide.
Silicon Specifications and Enterprise Workloads
Under the hood, raw execution capability is only part of the equation. The unnamed processor integrates specialized silicon blocks tailored for modern workloads:
- AI Inference Accelerators: Built directly onto the chip to handle in-transaction fraud detection without routing data off-die.
- Dedicated Data Processing Units (DPUs): On-chip hardware acceleration designed to offload heavy I/O operations from main processing cores.
- Large Cache Architecture: Expanded memory hierarchy engineered specifically to feed demanding enterprise workloads at clock speeds exceeding 5.7 GHz.
George Cozma, an analyst at TechInsights, noted that while the mainframe market remains small in unit terms, it holds immense strategic importance. Customers do not casually replace core systems. However, Cozma pointed out that the new processor represents an end to the platform’s historical isolation from the broader computing mainstream, aligning mission-critical security with modern software development lifecycles.
Historical Precedents in Dual-ISA Silicon
Building dual-architecture chips is not entirely new territory for IBM. During the mid-1990s, the computing veteran developed the PowerPC 615. That historic chip could run both PowerPC and x86 code natively, with the active instruction set architecture selected at boot time. Intended primarily for Apple during the clone era, the PowerPC 615 was ultimately never sold publicly.
Today’s effort differs fundamentally. Instead of selecting an ISA at boot, the upcoming 2nm chip executes Arm and Z instructions concurrently on the fly. This gives independent software vendors (ISVs) continuity while inviting mainframe-curious developers to target enterprise hardware using familiar cloud-native toolchains.
The Road to 2028
Commercial application vendors have historically been slow to prioritize z/OS. Major software providers know that the overall mainframe user base, while economically vital, is numerically small. For instance, modernization vendor Rocket Software noted that it is aware of just 42 IBM mainframe users in Australia alone, making it a targeted market.
With major hyperscalers building custom Arm processors and enterprise customers flocking to open-source infrastructure, IBM’s new silicon strategy addresses the platform’s divergence from modern software trends. If delivery stays on schedule for a 2028 rollout—prime timing to power potential z18 successors—Big Blue may successfully fuse the nine-nines resilience of the mainframe with the ubiquitous velocity of the Arm software ecosystem.
