SK Hynix has unveiled a new hardware architecture, the H-TPU (Hynix Transaction Processing Unit), designed to manage routine data tasks within storage devices.
The H-TPU system functions by fragmenting large data workloads into more than 100 autonomous, parallel operations. This distribution allows for high-speed processing directly within the storage controller, bypassing the need for the host CPU to manage minor operational details, as reported by Alkhabbar.
These units are built to support future high-speed standards, including the PCIe 8 interface. This protocol requires hardware capable of handling bandwidth up to 1 terabyte per second, or 1024 gigabytes per second, to prevent latency in data-intensive environments.
Each H-TPU core consumes approximately 2.5 percent of the energy required by a standard CPU core.
The architecture includes dynamic power management, allowing cores to be activated or deactivated based on real-time demand.
The rollout of H-TPU technology targets enterprise storage first, where servers must handle billions of concurrent operations per second.
| Feature | Traditional Controller | H-TPU Architecture |
|---|---|---|
| Physical Footprint | Standard size | 4% of traditional size |
| Power Consumption | Baseline | 2.5% per core (relative to CPU) |
Because the H-TPU units are fully programmable, developers can update their internal algorithms to match evolving file systems or database protocols without replacing physical hardware. This flexibility is expected to benefit professional media editing software, allowing for the smooth manipulation of high-resolution video files by offloading I/O management from the main system memory.
For students and researchers, the technology enables the execution of complex data simulations and mathematical models on standard hardware. By removing storage management tasks from the central processor, the system architecture maintains stability even during heavy multitasking, as detailed by Alkhabbar.
