Siemens Digital Industries Software announced its next-generation “AI-Native Design” strategy at the Siemens EDA Forum Seoul 2026, projecting that 70 percent of all chips will feature built-in AI accelerators by 2028. Driven by surging thermal densities exceeding 100W/cm² and transistor counts topping 200,000,000,000, the company is integrating autonomous agentic workflows across its entire Electronic Design Automation portfolio to mitigate soaring hardware validation bottlenecks.
The Four Macro-Trends Redefining Silicon Architecture
The semiconductor industry is undergoing a structural shift away from traditional, brute-force scaling. According to Siemens EDA, four primary macroeconomic and architectural trends are dictating this transformation:
- AI Everywhere: An estimated 70 percent of chips will integrate dedicated AI accelerators by 2028.
- Software-Defined Everything: Hardware implementation is determined by software.
- Heterogeneous Integration: Multi-die topologies and varied manufacturing nodes are being fused into single-package environments.
- Sustainability Imperative: Power efficiency has become a core benchmark.
Designing silicon under these parameters introduces unprecedented verification friction. Modern verification tasks consume the vast majority of total development cycles. To combat this, Siemens has invested over 25 billion euros into R&D for next-generation EDA and artificial intelligence tooling, helping drive a 19 percent revenue growth in the Digital Industries & Software division for the first half of 2026.
Autonomous Agentic AI and Hardware-Software Co-Verification
At the center of Siemens EDA’s hardware modernization push is a deeper strategic partnership with NVIDIA. The integration pairs Siemens’ proprietary Fuse EDA AI agent infrastructure with NVIDIA’s AI computing stacks, NeMo Gym, and the OpenShell sandbox security framework.
This architecture allows autonomous AI agents to interact directly with physical EDA engines, verifying architectural decisions and self-correcting errors. For instance, the Solido Characterization Suite Agent now operates at speeds up to 10 times faster, while cutting token costs by up to 5 times.
Meanwhile, the Questa One Agentic ToolKit utilizes goal-driven dedicated agents and context-aware intelligence to streamline smart logic verification. MediaTek research teams have already adopted these toolkits to reduce verification and task-training burdens.
Accelerating Multi-Billion Gate Verification with Veloce Systems
Hardware emulation sets the upper limit for modern system-on-chip design cycles. Siemens’ hardware-assisted verification line has absorbed these AI workflows directly to manage massive scale.
The Veloce proFPGA CS platform now validates multi-billion gate AI chips and complex chiplet architectures 10,000 times faster than existing methods. Similarly, the Veloce Strato CS emulation system was deployed to verify Arm’s upcoming AGI CPU Compute Subsystem (CSS), successfully completing full-chip validation runs on architectures exceeding 10 billion gates.
These hardware engines are no longer isolated accelerators. Siemens has woven these agentic capabilities throughout its entire software portfolio, including Catapult, Veloce-Innexis, Questa One, Aprisa, Solido, Calibre, Tessent, Xpedition, and HyperLynx.
The Asia-Pacific Silicon Hub and Regional Stakes
Addressing attendees at the Seoul forum, Ankur Gupta, Senior Vice President of the IC Product Division at Siemens EDA, highlighted the critical role of the Asia-Pacific market in global semiconductor manufacturing.
“Asia Pacific, and Korea in particular, is responsible for over 60 percent of global memory supply and is leading global AI chip innovation based on cutting-edge AI processors, High Bandwidth Memory, and advanced packaging,” Gupta stated. He pointed out that engineers are managing designs with over 200 billion transistors and thermal densities surpassing 100W/cm².
By connecting open ecosystems with comprehensive digital twin technologies, Siemens aims to link silicon dies, packaging layers, circuit boards, and complete systems into a unified digital thread. This infrastructure is designed to carry regional partners forward from raw AI hardware deployment into electrified transport and smart manufacturing applications.
