Siemens unveiled Tessent Silicon Executable software as a standalone application designed to translate test patterns and apply them directly onto high-speed interfaces and protocols. The platform bridges the gap between pre-silicon verification and physical production, targeting complex multi-die architectures and advanced semiconductor manufacturing demands.
Extending the Workflow Into Silicon Production
Semiconductor manufacturing faces a growing test content bottleneck. Modern device complexity, multi-die packaging, and advanced transistor technologies require precise test delivery methods to keep test times under control.
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Siemens Digital Industries Software designed Tessent Silicon Executable to handle this pressure by extending existing design-for-test workflows. The software consumes Tessent-generated test collateral, applies those patterns straight into the target execution environment, and funnels the results back down into established debug, diagnosis, and analysis pipelines.
“Semiconductor testing is at an inflection point requiring new scan test delivery methods while minimizing time-to-ramp for a product to release to market. The combination of silicon complexity, multi-die and new transistor technology is driving a growth in test content,” said Ankur Gupta, executive vice president and Head of IC, Siemens EDA, Siemens Digital Industries Software. Gupta added that embedding the software directly into automated test equipment connects test creation with execution, yielding optimized product economics for device manufacturing.
Ecosystem Collaborations With Advantest and Teradyne
Deploying new test methodologies across high-speed architectures demands hardware-level integration. Siemens launched the application in direct collaboration with major automated test equipment providers Advantest and Teradyne.
Advantest integrated the software into its V93000 platform using Link Scale, extending the capability into pre-silicon verification and DFT lab engineering through SiConic. “Advantest works with all major EDA vendors to address increasing device complexity and coverage gaps with a seamless workflow across the silicon lifecycle,” said Juergen Serrer, CTO of Advantest.
Teradyne targeted advanced packaging constraints by embedding the software into its UltraPort instrument for the UltraFLEXplus system. Shannon Poulin, president, Semiconductor Test group, Teradyne, noted that the integration provides a standard path to run SSN over PCIe for PCIe Gen 6 interfaces, reducing test times.
Addressing High-Speed Interface Testing Constraints
Traditional test mechanisms often struggle with signal integrity, longer test cycles, and high operating frequencies on modern silicon. Tessent Silicon Executable brings consistency across automated test equipment, bench setups, system-level test, and in-system environments.
By shortening the feedback loop between physical execution and diagnostic analysis, engineering teams can trace yield limiters faster without rebuilding test routines for each distinct phase of the product lifecycle. Further details and technical specifications on the yield learning application are available directly through the Siemens Tessent Silicon Executable product page.
